1. Field of the Invention
The present invention generally relates to controlling power states of memory devices in a memory system, and in particular, to a system and method for utilizing a combination of encoded commands and the presence of a selection mechanism to move the memory devices from one power state to another power state without the need for dedicated pins or wake-up commands. The memory devices may, for example, be dynamic random access memory (DRAM) devices.
2. Related Art
Computer systems often contain one or more integrated circuit (IC) chips that are coupled to memory modules using a memory interface, which provides communication between the IC chips and the memory modules. On the memory modules, there reside memory devices, such as DRAM devices. The IC chips may be memory controllers referred to as chipsets. In some systems, a processor such as the central processing unit (CPU) performs memory controller functions. As used herein, the term memory controller includes such a processor. Increasing demand for higher computer performance and capacity has resulted in a demand for larger memory. However, as the number of memory devices coupled to the memory controller increases, not only do costs of the system increase, but power consumed by operations within the memory devices also becomes significant. Even in their idle states, the memory devices drain power. In a laptop, this lessens the battery power. Moreover, when power is drained, it is converted into thermal energy, heating up components within the system, such as the memory devices and the memory controller. Oftentimes, a fan is provided in the system to dissipate heat, and the turning of the fan further drains power.
Prior art memory systems have implemented various methods to conserve power of a computer system by controlling power states of the memory devices. Specifically, when a memory device is sensed to be idle for a specific amount of time, the memory device is moved to a lower power state, such as a power-down state and a self-refresh state. For example, in a Synchronous DRAM (SDRAM) system, a dedicated pin is utilized as a power management feature on each DRAM, or a portion of the DRAM. FIG. 1 shows a timing diagram of a prior art SDRAM system that utilizes a dedicate clock enable (CKE) pin with a CKE signal 30 to control power states of each DRAM in the system. A low CKE signal 30 indicates that a DRAM(s) associated with the CKE signal 30 is to enter a low power state. A high CKE signal 30 indicates that a DRAM(s) associated with the CKE signal 30 is to exit a low power state. Besides a CKE signal 30, the timing diagram also shows commands 20, a chip select signal 10, and a power state 40. Based on a command sampled on commands 20 while the CKE signal 30 is low, the DRAM(s) associated with the CKE signal 30 enter different low power states. Based on commands sampled while the CKE signal 30 is high, the DRAM or DRAMs associated with the CKE signal 30 may exit from different low power states and/or enter different high power states. When chip select signal 10 is low, it selects a specific DRAM device or a bank of DRAM devices to receive a normal operation command. The power state 40 shows the power state of the DRAM(s) controlled by the particular CKE signal 30.
As illustrated in FIG. 1, the SDRAM system starts in an idle power state 41. A no-operation command (NOP) 22 is provided while the CKE signal 30 goes low, indicating that the DRAM is to enter a power-down state 42. Providing a different command for self-refresh while the CKE signal 30 is low indicates that the DRAM is to enter a self-refresh state, which dissipates even less power than in a power-down state. The DRAM stays in the power-down state 42 as long as CKE signal 30 remains low. When a high CKE signal 30 and a NOP 24 are sampled, the DRAM exits from the power-down state 42 and enters an active state 45. An exiting delay is associated with exiting a power-down state, where a memory has to wait for all its components to become fully powered before a command can be carried out. As a result, a normal operation command 26, such as a read, is not provided to the DRAM and the chip select 10 is not asserted to receive the command 26 until the exiting delay has elapsed. In certain situation, this results in pipeline stalls. Although the SDRAM system successfully uses dedicated pins, such as a CKE, as a power management feature, such usage is costly. In a common computer system, this would require four to eight dedicated pins on the memory controller to independently control the power states of all banks of DRAMs. Pins would also be required on the DRAMs for them to receive signals from the dedicated pins of the memory controller. More pins translate into more cost and more complication for a memory system.
A different approach is taken by prior art memory systems such as a Direct Rambus DRAM (Direct RDRAM) system. In the Direct RDRAM system, instead of using dedicated pins to control power states of the memory devices, dedicated commands are used to enter and exit low power states. In particular, an exit or wake-up command is required to exit from a low power state, such as a power-down state or a self-refresh state. Consequently, more complex logic must be implemented in the memory devices and the memory controllers to analyze and process the dedicated wake-up commands. This again translates into cost increases for a memory system. Therefore, there is a need for a system and method to control power states of a memory device with the reduction of dedicated pins and complication within a memory system.